Verilog

From Academic Kids

The Verilog HDL is a hardware description language, used for the design of ASICs and FPGAs in order to make digital circuits. The designers of Verilog wanted to design a language that was based on the C programming language so that it would be familiar to engineers and readily accepted. In practice, it bears only a vague resemblance to the C programming language, and probably resembles Pascal just as much.

The language differs from a conventional programming language in that the execution of program statements is not strictly linear. A Verilog model consists of a hierarchy of modules. Modules are defined with a set of inputs and outputs. For each module a list of wires, registers and submodules is defined. Also, within each module, statements, mostly grouped into execution blocks, define the behaviour of the module. Within a block, delineated with begin and end keywords, statements are executed in order, but all blocks in the design are executed in parallel.

A subset of the statements in the language is synthesizable. If the modules in the design contain only synthesizable statements, the design can often be transformed into the circuit layout of a computer chip using appropriate software.

Contents

History

Beginning

Verilog was first developed at Gateway Design Automation around 1984 as a hardware modeling language. Gateway Design Automation was later purchased by Cadence Design Systems in 1990. Cadence now had full proprietary rights to Gateway's Verilog and the Verilog-XL simulator logic simulators.

Standard Opened

With the increasing success of VHDL, Cadence moved down the Open Standards route. Cadence transferred Verilog into the public domain under the Open Verilog International (http://www.ovi.org) (OVI) (now known as Accellera) organization. Verilog was later submitted to IEEE and became IEEE Standard 1364-1995, commonly referred to as Verilog-95.

Verilog 2001

Extensions to Verilog-95 were submitted back to IEEE to cover the deficiencies that users had found in the original Verilog standard. These extensions became IEEE Standard 1364-2001 known as Verilog 2001

Superlog/System Verilog

The advent of High Level Verification languages such as OpenVera, and Verisity's E language encouraged the development of Superlog by Co-Design Automation Inc. Co-Design Automation Inc was later purchased by Synopsys. The foundations of Superlog and Vera have been donated to Accellera. It has been transformed and updated to SystemVerilog which will likely become the next IEEE standard.

The latest versions of the language include support for analog and mixed signal modelling. These are referred to as verilog-ams.

Example

An example counter circuit follows:

module Div20x (rst, clk, cet, cep, count,tc);
//TITLE   'Divide-by-20 Counter with enables'

//enable CEP is a clock enable only
//enable CET is a clock enable and enables the TC output

//a counter using the Verilog language

    parameter size = 5;
    parameter length = 20;

    input rst;  // These inputs/outputs represent connections to
    input clk;  // the module.  
    input cet;
    input cep;

    output [size-1:0] count; 
    output tc;

    reg [size-1:0] count;  // The reg declares storage-in hardware flip-flops
    wire tc;               // Wires are connections 
    
    // The always statement below is a parallel execution statement that
    // executes any time the signals rst or clk transition from low to high
    always @ (posedge rst or posedge clk) 
        begin                             
            if (rst)             // This simulates a reset of the counter                   
                count <= 5'b0;
            else if (cet && cep) // This simulates the enables both being true
            begin
                if (count == length-1)
                begin
                    count <= 5'b0;
                end
                else
                    count <= count + 5'b1;  // 5'b1 is 5 bits wide and 
            end                             // equal to the value 1.
        end

    // the value of tc is continuously assigned the value of the expression
    assign tc = (cet && (count == length-1));

endmodule

The "<=" operator in verilog is another aspect of its being a hardware description language as opposed to a normal procedural language. This is known as a "non-blocking" statement. When the simulation runs, all of the signals with a "<=" operator are evaluated in parallel. This is very similar to the behavior of a real flip-flop.

The other choice for assignment is an "=" operator and this is known as a blocking assignment. When the "=" operator is used, things occur in the sequence they occur much like a procedural language.

Example:
...
reg a, b, c, d;
wire e;
...
always @(b or e)
  begin
     a = b & e;
     b = a | b;
     #5 c = b;
     d = #6 c ^ e;
  end

The always clause above illustrates the other type of method of use, i.e. the always clause executes any time any of the entities in the list change, i.e. the b or e change. When one of these changes, immediately a and b are assigned new values. After a delay of 5 time units, c is assigned the value of b and the value of c ^ e is tucked away in an invisible store. Then after 6 more time units, d is assigned the value that was tucked away.

External links

fr:Verilog sv:Verilog zh:Verilog HDL

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